Zynq UltraScale+ MPSoC

SoCs with heterogeneous multi-processing engines for smarter systems

MPSOC Architecture Image.jpg
MPSOC Architecture Image.jpg

  • Quad-core Arm® Cortex®-A53
  • Dual-core Arm® Cortex®-R5
  • Arm® Mali-400 GPU
  • Programmable Logic

Xilinx Zynq UltraScale+ MPSoC

SoCs to enable true heterogeneous multi-processing with the right engines for the right tasks for smarter systems

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  • Cortex®-A53
    • Up to 4 x CPU frequency up to 1.5 GHz, NEON engine, 32 kB L1 Cache per CPU, 1MB L2 Cache (shared, 16-way associative)
  • Cortex®-R5
    • Up to 2 x CPU Frequency up to 600 MHz, lockstep-capable, 32 kB L1 Cache per CPU, 128 kB TCM with ECC per CPU
  • 256 kB On-Chip Memory
  • Multi-protocol memory controller, ECC, 8-Channel DMA Controller
  • Tri-speed Ethernet, PCI Express® Gen2, SATA 3.1, USB3.0, and DisplayPort
  • 2 x CAN,  2 x SD/SDIO 2.0/eMMC4.51, 2 x SPI
  • Two master and slave I2C interfaces
  • Arm AMBA® AXI4-based
  • RSA, AES, SHA
  • 47 to 502 LUTs
  • Block RAM, UltraRAM, DSP
  • 1.0 V to 3.3 V I/Os, LVCMOS, LVDS, SSTL.
  • PCI Express® Gen3
  • Video Encoder/Decoder, H.264, and H.265
  • 10-bit 200 kS/s ADC, up to 17 external inputs
  • Human Machine Interface
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